1. Field of the Invention
The present invention relates to a process for producing a substrate including therein an electronic component, such as a semiconductor element and a chip component.
2. Description of the Related Art
Demands for miniaturization and higher performance of electronic devices require a further reduction in the profile of components having a smaller mounting area. To meet such requirements, a component-embedded substrate is known in which multiple resin layers including a semiconductor element and a chip component therein are laminated.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2002-76637) discloses a process for producing the component-embedded substrate by press-bonding and transferring a supporting layer including a component-connected electrode pattern onto one surface of a prepreg, and then laminating the resulting prepreg with another prepreg in which a component is embedded by press bonding in a single step.
FIG. 8 is an example shown in FIG. 15 in Patent Document 1. In step (a), a prepreg 1501 including via holes 1502 and a supporting layer 1504 including an electrode pattern on which electronic components 1510 and 1511 are connected are prepared. In step (b), the prepreg 1501 and the supporting layer 1504 are laminated by press bonding. In step (c), the supporting layer 1504 is separated to form a wiring layer 1515. In step (d), the wiring layer 1515, another wiring layer 1514 in which an electronic component 1505 is embedded, wiring layers 1512 and 1513 including an electrode pattern 1506 and an interlayer via 1507, respectively, are laminated by press bonding in a single step to form a multilayer component-embedded substrate 1516 as shown in (e).
However, in such a single-step lamination process, at the interlayer between the laminated prepregs, an electrode pattern transferred on the surfaces of the prepregs is only in contact with another electrode pattern or an electronic component to provide an electrical connection. Thus, the connection resistance is disadvantageously increased, which results in insufficient connection reliability. Furthermore, since two electrode layers are disposed between the laminated prepregs, the bonding strength between the prepregs is low, thus possibly causing delamination.
To overcome these problems, in FIG. 16 in Patent Document 1, discloses a process in which a prepreg defining an adhesive layer including a through hole is provided between the cured resin layers to ensure the connection reliability between the electrode patterns or between the electrode pattern and the electronic component. However, this process disadvantageously requires an interlayer prepreg including no component. Thus, the thickness of the component-embedded substrate is increased.